The part of the paper(The LCI Lossless Image Compression
Algorithm:Principles and Standardization into JPEG-LS) that describes
the encoding of run length is not very analytic. Especially the
block-MELCDE algorithm. I search the papers [2],[7],[36],[46] via
Goolge but others are not accesible by me because I don't have
permission or are proprietary or Google did not find them. Do you know
where to find information about the subject?
thank you.

leonadavinci@gmail.com wrote:
The part of the paper(The LCI Lossless Image Compression
Algorithm:Principles and Standardization into JPEG-LS) that describes
the encoding of run length is not very analytic. Especially the
block-MELCDE algorithm. I search the papers [2],[7],[36],[46] via
Goolge but others are not accesible by me because I don't have
permission or are proprietary or Google did not find them. Do you know
where to find information about the subject?

thank you.

The document that you will want to implement JPEG-LS is the IS/IEC
standard 14495-1, which was also adopted by ANSI. Unfortunately, this
document will need to be purchased from the ANSI, IEC or IS web site.
We successfully implemented a lossless version of the algorithm in a
Xilinx FPGA from this document, so there is enough information, though
it might be light on the analysis. I did a quick text search, and the
word "Melcode" only shows up in the bibliography.

When we did this a number of years ago the draft version of the
specification was still available on the web (it my still be). I would
caution against using the draft to implement, as there were a number of
minor differences between the draft and the final specification that
will result in an encoding that is not compliant. It has been a few
years, so I do not remember what the exact differences were, but I seem
to recall one was marker removal, specifically how it is different than
IS/IEC 10918-1 (JPEG). But, if all you are looking for is more
information, the draft is virtually the same as the final.

I seem to recall that we had a much easier time following the IS/IEC
specification, than we did following the sample code that is out on the
web. We did use the sample code to generate our VHDL test benches, in
modifying it to spit out intermediary calculations, we did become
intimately involved. experience was that the path through the code
was not very linear due to some of the optimizations that it employed.
(I hope I do not offend the author with the previous statement, as the
code was well written as an implementation, just not so much as a
learning tool for the algorithm)

Regards,
Erik.

Erik Widding
President
Birger Engineering, Inc.

(mail) 100 Boylston St #1070; Boston, MA 02116
(voice) 617.695.9233
(fax) 617.695.9234
(web) http://www.birger.com